The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a plasma doping method performed on a substrate or a thin layer.
Typically, doping is performed to obtain a desirable electrical property of a substrate or a thin layer such as polysilicon during the fabrication of a semiconductor device. A beam line ion implantation method is mainly used as a doping method. The beam line ion implantation method uses an electrical field to accelerate ions to be implanted (i.e., provide high kinetic energy). The accelerated ions collide against a surface of a solid state material. As a result, the ions may be implanted into the substrate.
Recently, a plasma doping method has been used. In the plasma doping method, a source material for the ions to be implanted is in a gas state. A plasma is formed and then, a high voltage bias is applied to a sample to be doped. As a result, positive ions of the plasma accelerate into a surface of the sample and are implanted thereto. Accordingly, the plasma doping method may perform a uniform doping, and improve a doping rate. Furthermore, since the plasma doping method does not need to use a separate ion generating source (i.e., an ion beam) and acceleration apparatus as compared with the beam ion implantation method, an equipment fabrication cost may be reduced.
FIGS. 1A to 1C illustrate a typical method for fabricating a semiconductor device. As shown in FIG. 1A, a plurality of device isolation layers 12 are formed in sections of a substrate 11. A gate insulation layer 13 is formed over the substrate 11, and a gate polysilicon layer 14 is formed over the gate insulation layer 13. A plasma doping method is performed to dope the gate polysilicon layer 14 with a P-type impurity.
As shown in FIG. 1B, an anneal process is performed to activate the P-type impurity doping in the gate polysilicon layer 14.
As shown in FIG. 1C, a metal silicide layer such as a gate tungsten silicide layer 15 is formed over the gate polysilicon layer 14 and then, a gate patterning process is performed as a subsequent process. If the plasma doping method is performed according to the description above, an excessive concentration of impurities may exist over a top surface of a thin layer.
FIG. 2 is a graph illustrating typical profiles of impurities doped via a beam line ion implantation method and a plasma doping method onto a sample in which a gate polysilicon layer is formed. A horizontal axis represents a depth of the sample, and a vertical axis represents a concentration of boron, which is used as a P-type impurity. A depth of about 800 Å identifies a depth of an interface between a top surface of the gate oxide layer and a gate polysilicon layer. In more detail, a depth of the gate polysilicon layer is about 800 Å. With reference to FIG. 2, the impurity profile obtained via the plasma doping method is compared with that obtained via the ion implantation method. The impurity concentration is relatively larger at the top surface of the gate polysilicon layer (e.g., at a portion of the gate polysilicon layer corresponding to a depth of about 0 Å) when performing the plasma doping method than in the beam line ion implantation. Particularly, while the impurity concentration shows a Gaussian distribution at about 200 Å in the beam line ion implantation method, the impurity concentration is the largest at the top surface of the gate polysilicon layer in the plasma doping method.
FIG. 3 is a graph illustrating typical profiles of impurities doped via a beam line ion implantation method and plasma doping methods after an annealing process is performed. Reference denotations ▪ and ● represent different types of impurities used in the plasma doping methods. The impurity is activated down to a bottom surface of a gate polysilicon layer (e.g., around a top surface of a gate oxide layer) via the annealing process. In the case of performing the plasma doping methods, the largest impurity concentrations are measured at the top surface of the gate polysilicon layer, i.e., at a depth of about 0 Å of the gate polysilicon layer.
As shown in FIGS. 2 and 3, if the plasma doping methods are performed, a large amount of the impurity may exist over the top surface of the gate polysilicon layer although the annealing process is performed. The impurity existing over the top surface of the gate polysilicon layer is diffused out toward an upper layer of the gate polysilicon layer, e.g., a metal silicide layer, during a subsequent annealing process. Accordingly, a doping effect is abruptly reduced around the surface of the gate polysilicon layer. That is, a relative impurity depletion effect may be generated at the surface of the gate polysilicon layer. The reduction in the doping effect brings an increase in resistance of the gate polysilicon layer. Furthermore, a saturation current property of a P-type metal oxide semiconductor (PMOS) transistor having a gate formed of polysilicon doped with a P+-type impurity may be degraded.